A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI desi...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2009
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| Subjects: |