Design of a testchip for low cost IC testing.

With the continuous increase of the integration densities and complexities, the problem of testing integrated circuits has become much more acute and needs an economic solution with reliable performance. This paper presents the design of a TESTCHIP implementing a multiple polynomial, multiple seed b...

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Main Authors: Ali, Liakot, Sidek, Roslina, Aris, Ishak, Mohd Ali, Mohd Alauddin
Format: Article
Language:English
English
Published: Taylor & Francis 2009
Online Access:http://psasir.upm.edu.my/id/eprint/17691/1/Design%20of%20a%20testchip%20for%20low%20cost%20IC%20testing.pdf
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author Ali, Liakot
Sidek, Roslina
Aris, Ishak
Mohd Ali, Mohd Alauddin
author_facet Ali, Liakot
Sidek, Roslina
Aris, Ishak
Mohd Ali, Mohd Alauddin
author_sort Ali, Liakot
collection UPM
description With the continuous increase of the integration densities and complexities, the problem of testing integrated circuits has become much more acute and needs an economic solution with reliable performance. This paper presents the design of a TESTCHIP implementing a multiple polynomial, multiple seed based mixed-mode test technique. Fault simulation experiments on benchmark circuits show that the TESTCHIP is capable of detecting 100% of the faults using a much lower number of test vectors than in the approaches attempted by the other researchers. It also offers lower data storage requirements than that of conventional ATE. The TESTCHIP is capable of testing combinational circuits as well as sequential circuits with scan-path facilities.
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spelling upm.eprints-176912015-11-23T01:56:40Z http://psasir.upm.edu.my/id/eprint/17691/ Design of a testchip for low cost IC testing. Ali, Liakot Sidek, Roslina Aris, Ishak Mohd Ali, Mohd Alauddin With the continuous increase of the integration densities and complexities, the problem of testing integrated circuits has become much more acute and needs an economic solution with reliable performance. This paper presents the design of a TESTCHIP implementing a multiple polynomial, multiple seed based mixed-mode test technique. Fault simulation experiments on benchmark circuits show that the TESTCHIP is capable of detecting 100% of the faults using a much lower number of test vectors than in the approaches attempted by the other researchers. It also offers lower data storage requirements than that of conventional ATE. The TESTCHIP is capable of testing combinational circuits as well as sequential circuits with scan-path facilities. Taylor & Francis 2009 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/17691/1/Design%20of%20a%20testchip%20for%20low%20cost%20IC%20testing.pdf Ali, Liakot and Sidek, Roslina and Aris, Ishak and Mohd Ali, Mohd Alauddin (2009) Design of a testchip for low cost IC testing. Intelligent Automation and Soft Computing, 15 (1). pp. 63-72. ISSN 1079-8587 10.1080/10798587.2009.10643016 English
spellingShingle Ali, Liakot
Sidek, Roslina
Aris, Ishak
Mohd Ali, Mohd Alauddin
Design of a testchip for low cost IC testing.
title Design of a testchip for low cost IC testing.
title_full Design of a testchip for low cost IC testing.
title_fullStr Design of a testchip for low cost IC testing.
title_full_unstemmed Design of a testchip for low cost IC testing.
title_short Design of a testchip for low cost IC testing.
title_sort design of a testchip for low cost ic testing
url http://psasir.upm.edu.my/id/eprint/17691/1/Design%20of%20a%20testchip%20for%20low%20cost%20IC%20testing.pdf
work_keys_str_mv AT aliliakot designofatestchipforlowcostictesting
AT sidekroslina designofatestchipforlowcostictesting
AT arisishak designofatestchipforlowcostictesting
AT mohdalimohdalauddin designofatestchipforlowcostictesting