Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography
In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxid...
| Main Authors: | , , , , , , , , , |
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| Format: | Book Section |
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Trans Tech Publications
2013
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| _version_ | 1825947702866739200 |
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| author | Dehzangi, Arash Larki, Farhad Hassan, Jumiah Hutagalung, Sabar D. Saion, Elias Hamidon, Mohd Nizar Abdullah, A. Makarimi Kharazmi, Alireza Mohammadi, Sanaz Majlis, Burhanoddin Y. |
| author_facet | Dehzangi, Arash Larki, Farhad Hassan, Jumiah Hutagalung, Sabar D. Saion, Elias Hamidon, Mohd Nizar Abdullah, A. Makarimi Kharazmi, Alireza Mohammadi, Sanaz Majlis, Burhanoddin Y. |
| author_sort | Dehzangi, Arash |
| collection | UPM |
| description | In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode. |
| first_indexed | 2024-03-06T08:17:30Z |
| format | Book Section |
| id | upm.eprints-30416 |
| institution | Universiti Putra Malaysia |
| last_indexed | 2024-03-06T08:17:30Z |
| publishDate | 2013 |
| publisher | Trans Tech Publications |
| record_format | dspace |
| spelling | upm.eprints-304162015-07-24T03:32:28Z http://psasir.upm.edu.my/id/eprint/30416/ Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography Dehzangi, Arash Larki, Farhad Hassan, Jumiah Hutagalung, Sabar D. Saion, Elias Hamidon, Mohd Nizar Abdullah, A. Makarimi Kharazmi, Alireza Mohammadi, Sanaz Majlis, Burhanoddin Y. In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode. Trans Tech Publications 2013 Book Section PeerReviewed Dehzangi, Arash and Larki, Farhad and Hassan, Jumiah and Hutagalung, Sabar D. and Saion, Elias and Hamidon, Mohd Nizar and Abdullah, A. Makarimi and Kharazmi, Alireza and Mohammadi, Sanaz and Majlis, Burhanoddin Y. (2013) Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography. In: Nano Hybrids. Trans Tech Publications, pp. 93-113. ISBN 9783038358640 10.4028/www.scientific.net/NH.3.93 |
| spellingShingle | Dehzangi, Arash Larki, Farhad Hassan, Jumiah Hutagalung, Sabar D. Saion, Elias Hamidon, Mohd Nizar Abdullah, A. Makarimi Kharazmi, Alireza Mohammadi, Sanaz Majlis, Burhanoddin Y. Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography |
| title | Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography |
| title_full | Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography |
| title_fullStr | Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography |
| title_full_unstemmed | Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography |
| title_short | Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography |
| title_sort | fabrication of p type double gate and single gate junctionless silicon nanowire transistor by atomic force microscopy nanolithography |
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