Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications
A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI
2016
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| Online Access: | http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf |