Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation

Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation

This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gat...

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Bibliographic Details
Main Authors: Al-Hussaini, Khalid, Mohd Ali, Borhanuddin, Varahram, Pooria, Hashim, Shaiful Jahari
Format: Article
Language:English
Published: Springer 2017
Online Access:http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf

Internet

http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf

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