Effective implementation of AES-XTS on FPGA
This paper proposes an effective FPGA implementation for data storage encryption. Throughput, area and power consumption are the most important parameters to evaluate any FPGA implemented design. Our proposed design not only achieves a high throughput but also a considerable amount of throughput/are...
| Main Authors: | , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2011
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| Online Access: | http://psasir.upm.edu.my/id/eprint/68776/1/Effective%20implementation%20of%20AES-XTS%20on%20FPGA.pdf |