Pipelined fast Fourier transform (FFT) processor power optimization

Pipelined fast Fourier transform (FFT) processor power optimization

This paper presents the pipelined Fast Fourier Transform (FFT) processor power optimization. Pipelined FFT processor comprises of several sub-modules such as data buffer, shifter, and rotator (butterfly) which introduced power consumption to the circuit when in a hierarchical design. The objectives...

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Bibliographic Details
Main Authors: Mohd Hassan, Siti Lailatul, Sulaiman, Nasri, Abdul Halim, Ili Shairah, Ab Rahim, A'zraa Ahfzan, Abdullah, Noor Ezan
Format: Conference or Workshop Item
Language:English
Published: IEEE 2019
Online Access:http://psasir.upm.edu.my/id/eprint/78065/1/Pipelined%20fast%20Fourier%20transform%20%28FFT%29%20processor%20power%20optimization.pdf

Internet

http://psasir.upm.edu.my/id/eprint/78065/1/Pipelined%20fast%20Fourier%20transform%20%28FFT%29%20processor%20power%20optimization.pdf

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