VLSI implementation of full adder-subtractor design
Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the major concerns in order to develop an efficient electronic devices. Addition is commonly used arithmetic operation in most electronic system which requires high performance and low power consumption of f...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Medwell Publications
2017
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/5196/1/AJ%202017%20%28329%29%20VLSI%20implementation%20of%20full%20adder-subtractor%20design.pdf |