An optimization algorithm based on grid-graphs for minimizing interconnect delay in VLSI layout design
In this paper, we describe a routing optimization algorithm based on grid-graphs for application in a deep-submicron VLSI layout design. The proposed algorithm, named S-RABILA (for Simultaneous Routing and Buffer Insertion with Look-Ahead), constructs a maze routing path, simultaneously with buffer...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
University of Malaya
2009
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/12990/1/MohamedKhalilHani2009_AnOptimizationAlgorithmBasedOnGrid-Graphs.pdf |