Nano-scale VLSI clock routing module based on useful-skew tree algorithm
Clock routing is critical in nano-scale VLSI circuit design. Clock routing needs to be precise to minimize circuit delay. Clock signals are strongly affected by technology scaling, the long global interconnect lines become highly resistive as line dimensions are decreased. The control of clock skew...
| Hoofdauteurs: | , , , |
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| Formaat: | Artikel |
| Taal: | English |
| Gepubliceerd in: |
School of Postgraduate Studies, UTM
2006
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| Onderwerpen: | |
| Online toegang: | http://eprints.utm.my/1687/1/sh-nasir05_Nano_scale_VLSI.pdf |