Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET)
Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET) incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was sc...
| Main Authors: | , , |
|---|---|
| Format: | Conference or Workshop Item |
| Published: |
2007
|
| Subjects: |
| _version_ | 1796856002220392448 |
|---|---|
| author | Ismail, Razali M. N., Zul Atfyi Fauzan Saad, Ismail |
| author_facet | Ismail, Razali M. N., Zul Atfyi Fauzan Saad, Ismail |
| author_sort | Ismail, Razali |
| collection | ePrints |
| description | Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET) incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was scaled to get an optimized structure. An analysis of current-voltage (I-V) of 50 nm channel length (Lg) has been done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V and increase when VDS = 1.0 V. Consequently, the threshold voltage (VT) is increased accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better for MOSFET with DP as compared to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product. |
| first_indexed | 2024-03-05T18:36:58Z |
| format | Conference or Workshop Item |
| id | utm.eprints-24436 |
| institution | Universiti Teknologi Malaysia - ePrints |
| last_indexed | 2024-03-05T18:36:58Z |
| publishDate | 2007 |
| record_format | dspace |
| spelling | utm.eprints-244362017-08-03T00:40:01Z http://eprints.utm.my/24436/ Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) Ismail, Razali M. N., Zul Atfyi Fauzan Saad, Ismail TK Electrical engineering. Electronics Nuclear engineering Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET) incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was scaled to get an optimized structure. An analysis of current-voltage (I-V) of 50 nm channel length (Lg) has been done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V and increase when VDS = 1.0 V. Consequently, the threshold voltage (VT) is increased accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better for MOSFET with DP as compared to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product. 2007 Conference or Workshop Item PeerReviewed Ismail, Razali and M. N., Zul Atfyi Fauzan and Saad, Ismail (2007) Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET). In: International Workshop on Antenna Technology 2007, iWAT 2007, 21st-23rd March, 2007, United Kingdom. |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Ismail, Razali M. N., Zul Atfyi Fauzan Saad, Ismail Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title | Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title_full | Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title_fullStr | Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title_full_unstemmed | Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title_short | Scaling and numerical simulation analysis of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title_sort | scaling and numerical simulation analysis of 50nm mosfet incorporating dielectric pocket dp mosfet |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| work_keys_str_mv | AT ismailrazali scalingandnumericalsimulationanalysisof50nmmosfetincorporatingdielectricpocketdpmosfet AT mnzulatfyifauzan scalingandnumericalsimulationanalysisof50nmmosfetincorporatingdielectricpocketdpmosfet AT saadismail scalingandnumericalsimulationanalysisof50nmmosfetincorporatingdielectricpocketdpmosfet |