Second-stage tuning procedure for analogue CMOS design reuse methodology
Proposed is a two-stage analogue circuit design reuse methodology by extending existing fabrication process rescaling procedures with a follow-on systematic tuning procedure stage based on DC output voltage scaling. It increases the potential for design reuse with short-channel MOSFET circuit design...
Main Authors: | Adnan, A. F. B., A'ain, Abu Khairi, Marsono, Muhammad Nadzir, Kamisan, I. B., Grout, I. A. |
---|---|
Format: | Article |
Published: |
The Institution of Engineering and Technology
2012
|
Subjects: |
Similar Items
-
Systematic tuning procedure for analog design reuse methodology /
by: Ahmad Faisal Adnan, 1987- author, et al.
Published: (2014) -
Wide tuning-range CMOS VCO based on a tunable active inductor
by: Babaei Kia, Hojjat, et al.
Published: (2014) -
Systematic tuning procedure for analog design reuse methodology [electronic resource] /
by: Ahmad Faisal Adnan, 1987- author, et al.
Published: (2014) -
Systematic tuning procedure for analog design reuse methodology
by: Adnan, Ahmad Faisal
Published: (2014) -
Design approach for tune able CMOS active inductor
by: Rafiq, Sharman, et al.
Published: (2004)