A network-on-chip simulation framework for homogeneous multi-processor system-on-chip
This paper presents a Network-on-Chip (NoC) simulation framework at the Electronic System Level (ESL) design abstraction based on SystemC. The proposed ESL NoC framework extends the NIRGAM NoC simulator by integrating ARM Instruction Set Simulator (ISS) as its application Intellectual Property (IP)...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2011
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