A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model
Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm Optimization (PSO) for solving routing probl...
| Main Authors: | , , , , , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2011
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| Subjects: |