A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model
Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm Optimization (PSO) for solving routing probl...
| Main Authors: | , , , , , , , , |
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| Format: | Conference or Workshop Item |
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2011
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| _version_ | 1796858768657481728 |
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| author | Md. Yusof, Zulkifli Tan, Zhe Hong Zainal Abidin, Amar Faiz Abdul Salam, Mohammad Nazry Adam, Asrul Ahmed Mukred, Jameel Abdulla Khalil, Kamal Shaikh-Husin, N. Ibrahim, Zuwairie |
| author_facet | Md. Yusof, Zulkifli Tan, Zhe Hong Zainal Abidin, Amar Faiz Abdul Salam, Mohammad Nazry Adam, Asrul Ahmed Mukred, Jameel Abdulla Khalil, Kamal Shaikh-Husin, N. Ibrahim, Zuwairie |
| author_sort | Md. Yusof, Zulkifli |
| collection | ePrints |
| description | Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm Optimization (PSO) for solving routing problem in VLSI circuits. A two-step Binary Particle Swarm Optimization (BPSO) approach, which is based on BPSO, is chosen in this study to improve time delay through finding the best path of wire placement with buffer insertion from source to sink. The best path of wire placement is found in the first step by the first BPSO and then the second BPSO finds the best location of buffer insertion along the wire. A case study is taken to measure the performance of the proposed model and the result obtained compared to the previous PSO approach for VLSI routing. |
| first_indexed | 2024-03-05T19:17:20Z |
| format | Conference or Workshop Item |
| id | utm.eprints-45529 |
| institution | Universiti Teknologi Malaysia - ePrints |
| last_indexed | 2024-03-05T19:17:20Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | utm.eprints-455292017-08-30T07:46:35Z http://eprints.utm.my/45529/ A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model Md. Yusof, Zulkifli Tan, Zhe Hong Zainal Abidin, Amar Faiz Abdul Salam, Mohammad Nazry Adam, Asrul Ahmed Mukred, Jameel Abdulla Khalil, Kamal Shaikh-Husin, N. Ibrahim, Zuwairie TK Electrical engineering. Electronics Nuclear engineering Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm Optimization (PSO) for solving routing problem in VLSI circuits. A two-step Binary Particle Swarm Optimization (BPSO) approach, which is based on BPSO, is chosen in this study to improve time delay through finding the best path of wire placement with buffer insertion from source to sink. The best path of wire placement is found in the first step by the first BPSO and then the second BPSO finds the best location of buffer insertion along the wire. A case study is taken to measure the performance of the proposed model and the result obtained compared to the previous PSO approach for VLSI routing. 2011 Conference or Workshop Item PeerReviewed Md. Yusof, Zulkifli and Tan, Zhe Hong and Zainal Abidin, Amar Faiz and Abdul Salam, Mohammad Nazry and Adam, Asrul and Ahmed Mukred, Jameel Abdulla and Khalil, Kamal and Shaikh-Husin, N. and Ibrahim, Zuwairie (2011) A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model. In: CIMSIM 2011 - 3rd International Conference On Computational Intelligence, Modelling & Simulation, CIMSIM 2011. http://dx.doi.org/10.1109/CIMSim.2011.21 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Md. Yusof, Zulkifli Tan, Zhe Hong Zainal Abidin, Amar Faiz Abdul Salam, Mohammad Nazry Adam, Asrul Ahmed Mukred, Jameel Abdulla Khalil, Kamal Shaikh-Husin, N. Ibrahim, Zuwairie A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model |
| title | A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model |
| title_full | A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model |
| title_fullStr | A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model |
| title_full_unstemmed | A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model |
| title_short | A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model |
| title_sort | two step binary particle swarm optimization approach for routing in vlsi with iterative rlc delay model |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
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