Built-in self test power and test time analysis in on-chip networks
Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of v...
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| Format: | Article |
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Springer Science+Business Media New York
2015
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