Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
In this paper, we present a low cost, pipelined FPGA architecture of a Harris Corner Detector. The platform is Altera Cyclone IV on a DE2-115 development board. The pipeline is composed of multiple stages, between which data flows without temporary full-frame buffering. The architecture was tested u...
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| Format: | Conference or Workshop Item |
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Institute of Electrical and Electronics Engineers Inc.
2016
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