Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms
Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM)...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Published: |
Elsevier B.V.
2017
|
| Subjects: |