Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms
Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM)...
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| Format: | Article |
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Elsevier B.V.
2017
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| _version_ | 1796862528561610752 |
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| author | Sirkunan, J. Ooi, C. Y. Shaikh-Husin, N. Hau, Y. W. Marsono, M. N. |
| author_facet | Sirkunan, J. Ooi, C. Y. Shaikh-Husin, N. Hau, Y. W. Marsono, M. N. |
| author_sort | Sirkunan, J. |
| collection | ePrints |
| description | Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, HTM performance is application-specific and determined by version and conflict management configurations. Most previous HTM implementations for embedded system in literature were built on fixed version management that result in significant performance loss when transaction behaviour changes. In this paper, we propose a HTM targeted for embedded applications which is able to adapt its version management based on application behaviour at runtime. It is prototyped and analysed on Altera Cyclone IV platform. Random requests at different contention levels and different transaction sizes are used to verify the performance of the proposed HTM. Based on our experiments, lazy version management is able to obtain up to 12.82% speed-up compared to eager version management at high contention level. Meanwhile, eager version management obtains up to 37.84% speed-up compared to lazy version management at low contention. The adaptive mechanism is able to switch configuration at runtime based on applications behaviour for maximum performance. |
| first_indexed | 2024-03-05T20:12:59Z |
| format | Article |
| id | utm.eprints-76556 |
| institution | Universiti Teknologi Malaysia - ePrints |
| last_indexed | 2024-03-05T20:12:59Z |
| publishDate | 2017 |
| publisher | Elsevier B.V. |
| record_format | dspace |
| spelling | utm.eprints-765562018-04-30T13:32:39Z http://eprints.utm.my/76556/ Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms Sirkunan, J. Ooi, C. Y. Shaikh-Husin, N. Hau, Y. W. Marsono, M. N. TK Electrical engineering. Electronics Nuclear engineering Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, HTM performance is application-specific and determined by version and conflict management configurations. Most previous HTM implementations for embedded system in literature were built on fixed version management that result in significant performance loss when transaction behaviour changes. In this paper, we propose a HTM targeted for embedded applications which is able to adapt its version management based on application behaviour at runtime. It is prototyped and analysed on Altera Cyclone IV platform. Random requests at different contention levels and different transaction sizes are used to verify the performance of the proposed HTM. Based on our experiments, lazy version management is able to obtain up to 12.82% speed-up compared to eager version management at high contention level. Meanwhile, eager version management obtains up to 37.84% speed-up compared to lazy version management at low contention. The adaptive mechanism is able to switch configuration at runtime based on applications behaviour for maximum performance. Elsevier B.V. 2017 Article PeerReviewed Sirkunan, J. and Ooi, C. Y. and Shaikh-Husin, N. and Hau, Y. W. and Marsono, M. N. (2017) Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms. Journal of Systems Architecture, 73 . pp. 42-52. ISSN 1383-7621 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85009461089&doi=10.1016%2fj.sysarc.2016.12.006&partnerID=40&md5=c3137ad393030934ea9c17083a64cc28 DOI:10.1016/j.sysarc.2016.12.006 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Sirkunan, J. Ooi, C. Y. Shaikh-Husin, N. Hau, Y. W. Marsono, M. N. Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms |
| title | Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms |
| title_full | Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms |
| title_fullStr | Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms |
| title_full_unstemmed | Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms |
| title_short | Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms |
| title_sort | hardware transactional memory architecture with adaptive version management for multi processor fpga platforms |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
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