Skip to content
VuFind
English
Deutsch
Español
Français
Italiano
日本語
Nederlands
Português
Português (Brasil)
中文(简体)
中文(繁體)
Türkçe
עברית
Gaeilge
Cymraeg
Ελληνικά
Català
Euskara
Русский
Čeština
Suomi
Svenska
polski
Dansk
slovenščina
اللغة العربية
বাংলা
Galego
Tiếng Việt
Hrvatski
हिंदी
Հայերէն
Українська
Sámegiella
Монгол
Language
All Fields
Title
Author
Subject
Call Number
ISBN/ISSN
Tag
Find
Advanced
Using altera de1-soc: integrat...
Cite this
Text this
Email this
Print
Export Record
Export to RefWorks
Export to EndNoteWeb
Export to EndNote
Permanent link
Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter
Bibliographic Details
Main Author:
Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa
Format:
Article
Published:
2018
Holdings
Description
Similar Items
Staff View
Similar Items
Using altera DE1-SoC: hard processor system (HPS) and field programmable gate array (FPGA) cores for median filter /
by: Syed Ahmad Asyraf Syed Mustafa, 1995- , author, et al.
Published: (2018)
Using altera DE1-SoC: hard processor system (HPS) and field programmable gate array (FPGA) cores for median filter /
by: Syed Ahmad Asyraf Syed Mustafa, 1995- , author
Published: (2018)
Educational automatic test equipment (ATE) based on field programmable gate array (FPGA) /
by: Wong Chun Hou, 1994- , author, et al.
Published: (2018)
QYPS HPS Interconnect verification methodology for SOC FPGA
by: Loh , Tat Jen
Published: (2013)
High speed Programmable Logic Controller (PLC) processor on Field Programmable Gate Array (FPGA) /
by: Muhammad Hafizzie Borham, 1990- , author, et al.
Published: (2013)