Asymmetrical multilevel inverter topology with reduced power semiconductor devices
In this paper, a new single-phase asymmetrical multilevel inverter topology is proposed. The topology is capable of producing n-level output voltage with reduced device counts. It is achieved by arranging available switches and dc sources to obtain maximum combinations of addition and subtraction of...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2017
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| Subjects: |