A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology
The minimization of very large-scale integrated circuits is facing a great challenge as the demands of devices with low power, and high-performance characteristics have intensely increased. Achieving a downscaled embedded memory design with a low leakage power, high stability, and minimized area bec...
| Main Authors: | , , , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Published: |
2021
|
| Subjects: |