A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
Faculty of Electrical Engineering
2008
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| Subjects: |