Improvement of the Symmetry and Linearity of Synaptic Weight Update by Combining the InGaZnO Synaptic Transistor and Memristor

Improvement of the Symmetry and Linearity of Synaptic Weight Update by Combining the InGaZnO Synaptic Transistor and Memristor

Obtaining symmetrical and highly linear synapse weight update characteristics of analog resistive switching devices is critical for attaining high performance and energy efficiency of the neural network system. In this work, based on the two-terminal one transistor-one memristor (1T1M) block, the im...

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Sonraí bibleagrafaíochta
Príomhchruthaitheoirí: Tae Jun Yang, Jung Rae Cho, Hyunkyu Lee, Hee Jun Lee, Seung Joo Myoung, Da Yeon Lee, Sung-Jin Choi, Jong-Ho Bae, Dong Myong Kim, Changwook Kim, Jiyong Woo, Dae Hwan Kim
Formáid: Alt
Teanga:English
Foilsithe / Cruthaithe: IEEE 2024-01-01
Sraith:IEEE Access
Ábhair:
InGaZnO thin-film transistors
analog resistive switching synapse
symmetric and linear synaptic weight update
synaptic transistor
memristor
neural network
Rochtain ar líne:https://ieeexplore.ieee.org/document/10436646/

Ar líne

https://ieeexplore.ieee.org/document/10436646/

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