Power Saving for Hardware Accelerated Applications With Dynamical Processor Switching
Services that require both heavy-load computation and low-latency have been increasing. To meet these requirements, an increasing number of servers are equipped with hardware accelerators such as a Graphics Processing Unit (GPU) or Field Programmable Gate Array (FPGA). These hardware accelerators ca...
| Main Authors: | , , , , |
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| פורמט: | Article |
| שפה: | English |
| יצא לאור: |
IEEE
2024-01-01
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| סדרה: | IEEE Access |
| נושאים: | |
| גישה מקוונת: | https://ieeexplore.ieee.org/document/10643958/ |