Power Saving for Hardware Accelerated Applications With Dynamical Processor Switching

Power Saving for Hardware Accelerated Applications With Dynamical Processor Switching

Services that require both heavy-load computation and low-latency have been increasing. To meet these requirements, an increasing number of servers are equipped with hardware accelerators such as a Graphics Processing Unit (GPU) or Field Programmable Gate Array (FPGA). These hardware accelerators ca...

Fuld beskrivelse

Bibliografiske detaljer
Main Authors: Ko Natori, Ikuo Otani, Hikaru Harasawa, Shogo Saito, Kei Fujimoto
Format: Article
Sprog:English
Udgivet: IEEE 2024-01-01
Serier:IEEE Access
Fag:
Energy efficiency
low latency communication
hardware accelerator
vRAN
field programmable gate arrays (FPGAs)
Online adgang:https://ieeexplore.ieee.org/document/10643958/

Internet

https://ieeexplore.ieee.org/document/10643958/

Lignende værker