An area- and power-efficient FIFO with error-reduced data compression for image/video processing

Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents...

Täydet tiedot

Bibliografiset tiedot
Päätekijät:	Zeinolabedin, Seyed Mohammad Ali, Kim, Tony T., Zhou, Jun, Liu, Xin
Muut tekijät:	School of Electrical and Electronic Engineering
Aineistotyyppi:	Conference Paper
Kieli:	English
Julkaistu:	2015
Aiheet:	DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Linkit:	https://hdl.handle.net/10356/79393 http://hdl.handle.net/10220/25887

Internet

https://hdl.handle.net/10356/79393
http://hdl.handle.net/10220/25887

An area- and power-efficient FIFO with error-reduced data compression for image/video processing

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