Clock data recovery circuits
This thesis presents the design and circuit implementation of a Clock Continuous Mode 2.5Gbps Data Recovery (CDR) circuit. The CDR is based on a new proposed dual-loop CDR architecture that doesn’t require the need of a lock detector. The operation is discussed in the report. The Foundary Design kit...
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| Format: | Thesis |
| Language: | English |
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2011
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| Online Access: | http://hdl.handle.net/10356/43528 |